In the video signal processing art there is usually a single central processing unit that has control over a bus which couples all the components attached to the central processing unit. As a result, the transactions that can take place are very restricted because there is only the one processing unit performing the applications as well as controlling the graphics subsystem. This works well only for low resolution graphics applications. There are add on cards which allow some acceleration in the graphics controller chip. This improvement saves bandwidth and allows off-loading of some high level commands to the graphics subsystem. For example, the central processing unit may send commands to draw a line or to draw a rectangle and merely provide coordinates to the graphics subsystem. This permits acceleration of the process compared with sending pixel-by-pixel information.
At low resolution graphics this approach worked well enough. At higher resolution applications, however, the central processing unit may still be overwhelmed. Thus as graphics resolutions increased, it was possible to add acceleration in order to accelerate some of the graphics operation but it eventually reached a point where the actual bus bandwidth of a typical bus in a computer system could not sustain the very high update rate of graphics images. This is further complicated when video is added because video must be updated at thirty frames a second, and may require five to nine megabytes per second sustained bandwidth across a bus into the graphics subsystem.
The goal of attaining an integrated video/graphics system requires system architecture which balances the often conflicting requirements of video subsystems and graphics subsystems. For example, while increasing horizontal and vertical resolution is useful to graphics images, in digital video subsystems increasing horizontal and vertical resolution is very expensive and may not perceptibly change the image quality. Likewise, in graphics subsystems, the pixel depth, the number of simultaneous colors available, is not as important as it is for video systems. While sixteen bit near-true-color pixels are more than adequate for a graphics system, a video system may advantageously make use of twenty-four bit pixels.
The performance budget of a video processor in a digital video subsystem during playback is divided and used to perform two tasks: (1) creating the video image from a compressed data stream, and (2) copying/scaling the image to the display buffer. The performance budget of the video subsystem must be balanced between the copy/scale operation and the video decompression operation. Both operations must be performed thirty times a second for smooth, natural motion video. The division of the performance budget is usually done to worse case which results in an allocation of sufficient performance with the remaining performance being dedicated to the video decompression operation for a full screen motion video copy/scale operation. If the number of pixels and/or bytes that have to be written in the copy/scale operation are increased, the performance of the video decompression necessarily decreases. For increased resolution, for a predetermined level of video technology, a point is reached where the video image starts to degrade because the information content in the decompressed image is too low.
As noted above, the requirements for a graphics system include high horizontal and vertical resolution with shallow pixels. A graphics subsystem in which the display is one kilobyte by one kilobyte with eight bit clut pixels substantially meets the needs of all but the most demanding applications. In contrast, the requirements for the video system include the ability to generate twenty-four bit true color pixels with a minimum of bytes in the display buffer. A typical adequate graphics subsystem may have 352.times.240.times.24 bits in YUV format. Although this can be scaled up for full screen, for many applications full screen is not required.
Systems integrating a graphics subsystem display buffer with a video subsystem display buffer generally fall into two categories. The two types of approaches are known as single frame buffer architectures and dual frame buffer architectures.
The single frame buffer architecture is the most straight forward approach and consists of a single graphics controller, a single digital-to-analog converter and a single frame buffer. In its simplest form, the single frame buffer architecture has each pixel on the display represented by bits in the display buffer that are consistent in their format regardless of the meaning of the pixel on the display. In this architecture graphics pixels and video pixels are indistinguishable in the frame buffer memory. However, the single frame buffer architecture graphics/video subsystem, i.e. the single frame buffer architecture visual system, does not address the requirements of the video subsystem very well. Full screen motion video on the single frame buffer architecture visual system requires updating every pixel in the display buffer thirty times a second. This frame buffer is most likely on the order of 1280.times.1024.times.8 bits. Even without the burden of writing over thirty megabytes per second to the display buffer, eight bit video by itself does not provide the required video quality. This means the single frame buffer architecture system can either move up to sixteen bits per pixel or implement the eight bit YUV subsampled technique.
A visual system must be able to mix video and graphics together on a display which requires the display to show on occasion a single video pixel located between graphics pixels. Because of the need to mix video and graphics every pixel in the display buffer must be a stand-alone, self-sustaining pixel on the screen.
It is an object of the present invention to provide an integrated system for storing and displaying graphics and video information.
It is further object of the present invention to provide a system for storing and displaying either graphics or video information, which system can be scalably upgraded into an integrated system for storing and displaying graphics and video information.
Further objects and advantages of the invention will become apparent from the description of the invention which follows.